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EVB7122 27 to 930mhz transceiver evaluation board description 39012 07122 02 page 1 of 24 evb description rev. 005 june/07 features ! single chip solution with only a few external components ! stand-alone fixed-frequency user mode ! programmable multi-channel user mode ! low current consumption in active mode and very low standby current ! pll-stabilized rf vco (lo) with internal varactor diode ! lock detect output in programmable user mode ! on-chip afc for extended input frequency acceptance range ! fsk for digital data or fm for analog signal reception ! fsk/ask mode selection ! rssi output for signal strength indication and ask reception ! ask detection normal or with peak detector ! switchable lna gain for improved dynamic range ! automatic pa turn-on after pll lock ! ask modulation achieved by pa on/off keying ! 3wire bus serial control interface ! evb comes with a cable to connect to a pc?s lpt port ! evb programming software is available on melexis web site ordering information part no. (see paragraph 6) EVB7122-315-fsk-c EVB7122-868-fsk-c EVB7122-433-fsk-c EVB7122-915-fsk-c note 1: evb default population is fsk, ask modifications according to section 4.2 and 4.3. note 2: EVB7122 is applicable for devices th7122 and th71221. application examples ! general bi-directional half duplex digital data rf signaling or analog signal communication ! tire pressure monitoring systems (tpms) ! remote keyless entry (rke) ! low-power telemetry systems ! alarm and security systems ! wireless access control ! garage door openers ! networking solutions ! active rfid tags ! remote controls ! home and building automation evaluation board example general description the th7122 is a single chip fsk/fm/ask transceiver ic. it is designed to operat e in low-power multi- channel programmable or single-channel stand-alone, hal f-duplex data transmission systems. it can be used for applications in automotive, i ndustrial-scientific-medical (ism), s hort range devices (srd) or similar applications operating in the frequency range of 300 mh z to 930 mhz. in programmable user mode, the transceiver can operate down to 27 mhz by em ploying an external vco varactor diode.
EVB7122 27 to 930mhz transceiver evaluation board description 39012 07122 02 page 2 of 24 evb description rev. 005 june/07 document content 1 theory of op eration ................................................................................................... 3 1.1 general........................................................................................................................ ..... 3 1.2 technical data overview.................................................................................................. 3 1.3 note on ask operation .................................................................................................... 3 1.4 block diagram .................................................................................................................. 4 1.5 user mode features ......................................................................................................... 4 2 description of user modes........................................................................................ 5 2.1 stand-alone user mode operation ................................................................................... 5 2.1.1 frequency sele ction ............................................................................................................ ........ 5 2.1.2 operati on m ode ................................................................................................................. .......... 5 2.1.3 modulati on ty pe ................................................................................................................ .......... 6 2.1.4 lna gain mode .................................................................................................................. ......... 6 2.2 programmable user mode operation............................................................................... 6 2.2.1 serial control inte rface descr iption ........................................................................................... .. 6 3 register d escription .................................................................................................. 7 3.1 register overview ............................................................................................................ 8 3.1.1 default register setti ngs for fs 0, fs1........................................................................................ 8 3.1.2 a ? wo rd ....................................................................................................................... ................ 9 3.1.3 b ? wo rd ....................................................................................................................... .............. 10 3.1.4 c ? wo rd....................................................................................................................... .............. 11 3.1.5 d ? wo rd....................................................................................................................... .............. 12 4 application circuits ................................................................................................. 13 4.1 fsk application circuit programmable user mode (internal afc option)...................... 13 4.1.1 board component values for fsk re ception ........................................................................... 14 4.1.2 component arrangement top si de for fsk re ception ............................................................ 15 4.2 ask application circuit programmable user mode (normal data slicer option) ............. 16 4.2.1 board component values for ask (normal data s licer opt ion) ................................................. 17 4.2.2 component arrangement top side for ask rec eption (normal data slicer option) ................. 18 4.3 ask application circuit with peak detector option ........................................................ 19 4.3.1 board component values for ask (peak detec tor opt ion)........................................................ 20 4.3.2 component arrangement top side for ask reception (peak detector option)........................ 21 5 evaluation boar d layouts ....................................................................................... 22 6 board va riants.......................................................................................................... 22 7 package descr iption ................................................................................................ 23 7.1 soldering information ..................................................................................................... 23 8 disclai mer ................................................................................................................. 24
EVB7122 27 to 930mhz transceiver evaluation board description 39012 07122 02 page 3 of 24 evb description rev. 005 june/07 1 theory of operation 1.1 general the main building block of the transceiver is a pr ogrammable pll frequency synthesizer that is based on an integer-n topology. the pll is used for generati ng the carrier frequency during transmission and for generating the lo signal during reception. the ca rrier frequency can be fsk-modulated by pulling the crystal and ask-modulated by on/off keying of the power am plifier. the receiver is based on the principle of a single conversion superhet. therefore the vco frequency has to be changed between transmit and receive mode. in receive mode, the preferr ed lo injection type is low-side injection. the th7122 transceiver ic consists of the following building blocks: " low-noise amplifier (lna) for high-sensitivity rf signal reception with switchable gain " mixer (mix) for rf-to-if down-conversion " if amplifier (ifa) to amplify and limit the if signal and for rssi generation " phase-coincidence demodulator with external ceramic discriminator (fsk demodulator) " operational amplifier (oa1), connected to demodulator output " operational amplifier (oa2), for geral use " peak detector (pkdet) for ask detection " control logic with 3wire bus serial control interface (sci) " reference oscillator (ro) with external crystal " reference divider (r counter) " programmable divider (n/a counter) " phase-frequency detector (pfd) " charge pump (cp) " voltage controlled oscillator (vco) with internal varactor " power amplifier (pa) with adjustable output power 1.2 technical data overview ! frequency range: 300 mhz to 930 mhz in programmable user mode ! extended frequency range with external vco varactor diode: 27 mhz to 930 mhz ! 315 mhz, 433 mhz, 868 mhz or 915 mhz fixed- frequency settings in stand-alone mode ! power supply range: 2.2 v to 5.5 v ! temperature range: -40 c to +85 c ! standby current: 50 na ! operating current in receive: 6.5 ma (low gain) ! operating current in transmit: 12 ma (at -2 dbm) ! adjustable rf power range: -20 dbm to +10dbm ! sensitivity: -105 dbm at fsk with 180 khz if filter bw ! sensitivity: -107 dbm at ask with 180 khz if filter bw ! max. data rate with crystal pulling: 20 kbps nrz ! max. data rate with direct vco modulation: 115 kbps nrz ! max. input level: -10 dbm at fsk and -20 dbm at ask ! input frequency acceptance: 10 to 150 khz (depending on fsk deviation) ! fm/fsk deviation range: 2.5 to 80 khz ! analog modulation frequency: max. 10 khz ! crystal reference frequency: 3 mhz to 12 mhz ! external reference frequency: 1 mhz to 16 mhz 1.3 note on ask operation optimum ask performance can be achieved by using an 8-mhz crystal for operation at 315 mhz, 434 mhz and 915 mhz. for details please refer to the software se ttings shown in sections 4.2 and 4.3. fsk operation is the preferred choice for applic ations in the european 868mhz band. for more detailed information, please refer to the latest th7122 data sheet revision
EVB7122 27 to 930mhz transceiver evaluation board description 39012 07122 02 page 4 of 24 evb description rev. 005 june/07 1.4 block diagram fig. 1: th7122 block diagram 1.5 user mode features the transceiver can operate in two different user modes. it can be used either as a 3wire-bus-controlled programmable or as a stand-alone fixed-frequency device. after power up, the transceiver is set to stand- alone user mode (sum). in this mode, pins fs0/sden and fs1/ld must be connected to v ee or v cc in order to set the desired frequency of operation. there are 4 pre-defined frequency settings: 315mhz, 433.92mhz, 868.3mhz and 915mhz. the logic level at pin fs0/sden must not be changed after power up in order to remain in fixed-frequency mode. after the first logic level change at pin fs0/sden, the transceiver enters into programmable user mode (pum). in this mode, the user can set any pll fr equency or mode of operation by the sci. in sum pins fs0/sden and fs1/ld are used to set the desired frequenc y, while in pum pin fs0/sden is part of the 3-wire serial control interface (sci ) and pin fs1/ld is the look detector output signal of the pll synthesizer. a mode control logic allows several operating modes. in addition to standby, transmit and receive mode, two idle modes can be selected to run either the referenc e oscillator only or the whole pll synthesizer. the pll settings for the pll idle mode are taken over from t he last operating mode which can be either receive or transmit mode. the different operating modes can be set in sum and pum as well. in sum the user can program the transceiver via control pins re/sclk and te/sdta. in pum the register bits opmode are used to select the modes of operation while pins re /sclk and te/sdta are part of the sci. in_lna lna gain_lna out_lna in_mix if mix 26 29 28 30 out_mix in_ifa vee_if 32 31 1 vee_lna 27 ifa vcc_if 2 rssi 7 1.5pf in_dem 3 mix demodulator fsk out_dta oa2 bias out_dem sw1 sw2 6 oa1 8 int1 5 int2/pdo 4 200k v ee_pll out_pa fsk ask lo in_dta ask/fsk re/sclk te/sdta fs0/sden 25 ps_pa 24 fsk_sw fs1/ld vee_ro 11 19 9 17 16 15 13 12 ro ro r counter n counter ro 10 sclk sdt a sden control logic sci pkdet vco pa vcc_pll 20 tnk_lo 23 22 lf 21 18 vee_dig 14 vcc_dig
EVB7122 27 to 930mhz transceiver evaluation board description 39012 07122 02 page 5 of 24 evb description rev. 005 june/07 2 description of user modes 2.1 stand-alone user mode operation after power up the transceiver is set to stand-alone us er mode. in this mode, pins fs0/sden and fs1/ld must be connected to v ee or v cc to set the desired frequency of operation. the logic level at pin fs0/sden must not be changed after power up in order to remain in stand-alone user mode. the default settings of the control word bits in stand-alone user mode are de scribed in the frequency selection table. detailed information about the default settings can be found in the tables of section 5. 2.1.1 frequency selection channel frequency 433.92 mhz 868.3 mhz 315 mhz 915 mhz fs0/sden 1 0 1 0 fs1/ld 0 0 1 1 reference oscillator frequency 7.1505 mhz r counter ratio in rx mode (rr) 32 16 18 32 pfd frequency in rx mode 223.45 khz 446.91 khz 397.25 khz 223.45 khz n counter ratio in rx mode (nr) 1894 1919 766 4047 vco frequency in rx mode 423.22 mhz 857.60 mhz 304.30 mhz 904.30 mhz rx frequency 433.92 mhz 868.30 mhz 315.00 mhz 915.00 mhz r counter ratio in tx mode (rt) 32 16 18 32 pfd frequency in tx mode 223.45 khz 446.91 khz 397.25 khz 223.45 khz n counter ratio in tx mode (nt) 1942 1943 793 4095 vco frequency in tx mode 433.92 mhz 868.30 mhz 315.00 mhz 915.00 mhz tx frequency 433.92 mhz 868.30 mhz 315.00 mhz 915.00 mhz if in rx mode 10.7 mhz 10.7 mhz 10.7 mhz 10.7 mhz in stand-alone user mode, the transceiver can be set to standby, receive, transmit or idle mode (only pll synthesizer active) via control pins re/sclk and te/sdta. the modulation scheme and the lna gain are set by pins ask/fsk and ga in_lna, respectively. 2.1.2 operation mode operation mode standby receive transmit idle re/sclk 0 1 0 1 te/sdta 0 0 1 1 note: pins with internal pull-down
EVB7122 27 to 930mhz transceiver evaluation board description 39012 07122 02 page 6 of 24 evb description rev. 005 june/07 2.1.3 modulation type modulation type ask fsk ask / fsk 0 1 2.1.4 lna gain mode lna gain high low gain_lna 0 1 2.2 programmable user mode operation the transceiver can also be used in programmable user mode. after power-up the first logic change at pin fs0/sden enters into this mode. now full programmab ility can be achieved via the serial control interface (sci). 2.2.1 serial control interface description a 3-wire (sclk, sdta, sden) serial control interface (sci) is used to program the transceiver in program- mable user mode. at each rising edge of the sclk signal, the logic value on the sdta pin is written into a 24-bit shift register. the data stored in the shift regi ster are loaded into one of the 4 appropriate latches on the rising edge of sden. the control words are 24 bits lengths: 2 address bits and 22 data bits. the first two bits (bit 23 and 22) are latch address bits. as additional leading bits are ignored, only the least significant 24 bits are serial-clocked into the shift register. the fi rst incoming bit is the most significant bit (msb). to program the transceiver in multi-channel application, f our 24-bit words may be sent: a-word, b-word, c-word and d-word. if individual bits within a word have to be changed, then it is sufficient to program only the appropriate 24-bit word. the serial data input timing and t he structure of the contro l words are illustrated in fig. 2 and 3. fig. 2: sci block diagram a - latch addr decoder b - latch c - latch d - latch 22 a-word 22 22 ?? 00 ?? 10 ?? 11 ?? 01 2 22 22 22 22 b-word 22 d-word 22 c-word 24-bit shift register sden sdta sclk
EVB7122 27 to 930mhz transceiver evaluation board description 39012 07122 02 page 7 of 24 evb description rev. 005 june/07 due to the static cmos design, the sci consumes vi rtually no current and it can be programmed in active as well as in standby mode. if the transceiver is set from standby mode to any of the active modes (idle, receive, transmit), the sci settings remain the same as previously set in one of the active modes, unless new settings are done on the sci while entering into an active mode. fig. 3: serial data input timing 3 register description as shown in the previous section t here are four control words which sti pulate the operation of the whole chip. in stand-alone user mode sum the intrinsic default values with respect to the applied levels at pins fs0 and fs1 lay down the configuration of the transceiver. in programmable user mode (pum) the register settings can be changed via 3-wire interface sci. the default settings which vary with the desired operating frequency depend on the voltage levels at the frequency se lection pins fs0 and fs1 before entering the pum. table 5.1.1 shows the default r egister settings of different frequenc y selections. it should be noted that the channel frequency listed below will be achieved with a crystal frequency of 7.1505 mhz. the following table depicts an overview of the regi ster configuration of the th7122. t es t cwl t cs t cwh t ch t ew t eh sden sdta bit 23 bit 22 bit 1 bit 0 msb invalid data invalid data lsb sclk
EVB7122 27 to 930mhz transceiver evaluation board description 39012 07122 02 page 8 of 24 evb description rev. 005 june/07 3.1 register overview word data msb lsb 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit no. 0 0 0 0 0 0 0 1 1 1 1 1 0 0 depends on fs0/fs1 voltage level after power up default a idle datapol modsel cpcur lockmode pactrl txpower [ 1 :0 ] set to 1 lnagain opmode [ 1 : 0 ] rr [ 9 : 0 ] 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit no. 0 1 0 1 1 1 0 0 1 1 1 0 1 0 depends on fs0/fs1 voltage level after power up default b pkdet set to 1 delpll lnahyst afc oa2 romax [ 2 : 0 ] romin [ 2 : 0 ] rt [ 9 : 0 ] 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit no. 1 0 0 0 depends on fs0/fs1 voltage level after power up default c lnactrl pfdpol vcocur [ 1 :0 ] band nr [ 16 : 0 ] 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit no. 1 1 0 0 1 0 0 depends on fs0/fs1 voltage level after power up default d modctrl ldtm [ 1 :0 ] ertm [ 1 :0 ] nt [ 16 : 0 ] 3.1.1 default register settings for fs0, fs1 fs1 fs0 channel frequency band vcocur [ 1 : 0 ] rr [ 9 : 0 ] nr [ 16 :0 ] rt [ 9 :0 ] nt [ 16 : 0 ] 0 0 868.30 mhz 1 11 16d 1919d 16d 1943d 0 1 433.92 mhz 0 01 32d 1894d 32d 1942d 1 0 915.00 mhz 1 11 32d 4047d 32d 4095d 1 1 315.00 mhz 0 00 18d 766d 18d 793d note: d ? decimal code a detailed description of the registers function and thei r configuration can be found in the following sections.
EVB7122 27 to 930mhz transceiver evaluation board description 39012 07122 02 page 9 of 24 evb description rev. 005 june/07 3.1.2 a ? word name bits description reference divider ratio in rx operation mode rr [9:0] 4d .. 1023d operation mode opmode [11:10] 00 01 10 11 standby mode receive mode transmit mode idle mode #default lna gain 0 1 low lna gain high lna gain #default lnagain [12] this selection is valid if bit lnactr (bit 21 in c-word) is set to internal lna gain control. not used [13] set to ?1? for correct function output power steps txpower [15:14] 00 01 10 11 p1 p2 p3 p4 #default set the pa-on condition pactrl [16] 0 1 pa is switched on if the pll locks pa is always on in tx mode #default set the pll locked state observation mode 0 before lock only #default locked state condition will be ascertained only one ti me afterwards the ld signal remains in high state. 1 before and after lock lockmode [17] locked state will be observed permanently charge pump output current cpcur [18] 0 1 260 a 1300 a #default modulation mode 0 1 ask fsk #default modsel [19] this selection is valid if bit modctrl (bit 21 in d-word) is set to internal modulation control. input data polarity 0 normal #default ?0? for space at ask or f min at fsk, ?1? for mark at ask or f max at fsk 1 inverse dtapol [20] ?1? for space at ask or f min at fsk, ?0? for mark at ask or f max at fsk active blocks in idle mode idlesel [21] 0 1 only ro active whole pll active #default
EVB7122 27 to 930mhz transceiver evaluation board description 39012 07122 02 page 10 of 24 evb description rev. 005 june/07 3.1.3 b ? word name bits description reference divider ratio in tx operation mode rt [9:0] 4d .. 1023d set the desired steady state current of the reference oscillator romin [12:10] 000 001 010 011 100 101 110 111 0 a 75 a 150 a 225 a 300 a 375 a 450 a 525 a #default the control circuitry regulates t he current of the oscillator core between the values romax and romin. as the regulation input signal the amplitude on pin ro is used. if the romin value is sufficient to achieve an amplitude of about 400mv on pin ro the current of the reference oscillator core will be set to romin. otherwise the current will be permanently regulated between romax and romin. if romin and romax are equal no regulation of the oscillator current occurs. please also note the block description of the reference oscillator in para. 3.1.1 set the start-up current of the reference oscillator romax [15:13] 000 001 010 011 100 101 110 111 0 a 75 a 150 a 225 a 300 a 375 a 450 a 525 a #default set the start-up current of the reference oscillator core. please also note the description of the romin register and the block description of the reference oscillator which can be seen above. oa2 operation 0 1 disabled enabled #default oa2 [16] oa2 can be enabled in fsk receive mode. oa2 is disabled in ask mode receive. internal afc feature 0 1 disabled enabled #default afc [17] hysteresis on pin gain_lna lnahyst [18] 0 1 disabled enabled - typical 340 mv (v 0 1 = 1.56v, v 1 0 = 1.22v) #default delayed start of the pll 0 undelayed start pll starts at the reference oscillator start-up 1 starts after 8 valid ro-cycles #default delpll [19] pll starts after 8 valid ro-cycles before enter ing an active mode to ens ure reliable oscillation of the reference oscillator. not used [20] set to ?1? for correct function rssi peak detector 0 disabled #default the rssi output signal directly feeds t he data slicer setup by means of oa1. 1 enabled pkdet [21] in ask receive mode the rssi peak detector output is multiplexed to pin int2/pdo.
EVB7122 27 to 930mhz transceiver evaluation board description 39012 07122 02 page 11 of 24 evb description rev. 005 june/07 3.1.4 c ? word name bits description feedback divider ratio in rx operation mode nr [16:0] 64d .. 131071d set the desired frequency range 0 1 recommended at f rf < 500 mhz recommended at f rf > 500mhz band [17] some tail current sources are linked to this bit in order to save current for low frequency operations. vco active current vcocur [19:18] 00 01 10 11 low current (300 a) standard current (500 a) high1 current (700 a) high2 current (900 a) phase detector polarity pfdpol [20] 0 1 negative #default positive neg pos frequency output vco vco input voltage lna gain control mode 0 external lna gain control #default lna gain will be set via pin gain_lna. 1 internal lna gain control lnactrl [21] lna gain will be set via bit lnagain (bit 12 in a-word). nevertheless pin gain_lna must be connected to either vcc or vee.
EVB7122 27 to 930mhz transceiver evaluation board description 39012 07122 02 page 12 of 24 evb description rev. 005 june/07 3.1.5 d ? word name bits description feedback divider ratio in tx operation mode nt [16:0] 64d .. 131071d set the unlock condition of the pll ertm [18:17] 00 01 10 11 2 clocks 4 clocks 8 clocks 16 clocks #default set the maximum allowed number of reference clocks (1/f ro ) during the phase detector output signals (up & down) can be in-consecutive. set the lock condition of the pll ldtm [20:19] 00 01 10 11 4 clocks 16 clocks 64 clocks 256 clocks #default set the minimum number of consecutive edges of phase detector output cycles, without appearance of any unlock condition. set mode of modulation control: 0 external modulation control #default modulation will be set via pin ask/fsk. 1 internal modulation control modctrl [21] modulation will be set via bit modsel (bit 19 in a-word). nevertheless pin ask/fsk must be connected to either vcc or vee.
EVB7122 27 to 930mhz transceiver evaluation board description 39012 07122 02 page 13 of 24 evb description rev. 005 june/07 4 application circuits 4.1 fsk application circuit programmabl e user mode (internal afc option) cb7 rs3 rs2 rs1 crx0 41 2 3 gnd sdta sden sclk 41 2 3 gnd gnd out_dta in_dta out_dem 41 2 3 gnd gnd rssi gnd vcc 1 2 cb0 ctx0 fs0/sden te/sdta re/sclk ask/fsk fs1/ld 2 1 3 2 1 3 2 1 3 2 1 3 2 1 3 cb2 rf cf1 cf2 ltx0 lrx2 ctx4 l0 c0 cb6 32 31 30 29 28 27 26 25 fs0/sden tnk_lo in_dta ask/fsk vcc_dig re/sclk gain_lna vee_if in_mix out_mix out_pa out_lna vee_lna vcc_pll vee_dig vee_pll lf fs1/ld 17 18 19 20 21 22 23 24 12 13 14 15 16 1 2 in_lna vcc_if th7122 rps xtal cx1 c5 c4 cx2 c3 in_dem int2/pdo int1 out_dem rssi out_dta ro fsk_sw vee_ro 9 10 11 8 3 4 5 6 7 cb5 rp rl0 cerdis cb4 cerfil tx_out rx_in 50 ctx2 ctx1 ltx1 l1 c1 c2 vcc cb1 vcc rb1 in_ifa
EVB7122 27 to 930mhz transceiver evaluation board description 39012 07122 02 page 14 of 24 evb description rev. 005 june/07 4.1.1 board component values for fsk reception part size value @ 315 mhz value @ 433.92 mhz value @ 868.3 mhz value @ 915 mhz tol. description c0 0603 0.47 pf nip 1.8 pf 1.5 pf 5% vco tank capacitor c1 0603 3.9 pf 4.7 pf 1.8 pf 1 pf 5% lna output tank capacitor c2 0603 1.5 pf 1.5 pf 1.5 pf 1.5 pf 5% mix input matching capacitor c3 0603 10 nf 10 nf 10 nf 10 nf 10% data slicer capacitor c4 0603 330 pf 330 pf 330 pf 330 pf 5% demodulator output low-pass capacitor, depending on data rate c5 0603 1.5 nf 1.5 nf 1.5 nf 1.5 nf 10% rssi output low pass capacitor cb0 1210 10 f 10 f 10 f 10 f 20% de-coupling capacitor cb1 0603 10 nf 10 nf 10 nf 10 nf 10% de-coupling capacitor cb2 0603 330 pf 330 pf 330 pf 330 pf 10% de-coupling capacitor cb4 0603 10 nf 10 nf 10 nf 10 nf 10% de-coupling capacitor cb5 0603 100 nf 100 nf 100 nf 100 nf 10% de-coupling capacitor cb6 0603 100 pf 100 pf 100 pf 100 pf 10% de-coupling capacitor cb7 0603 100 nf 100 nf 100 nf 100 nf 10% de-coupling capacitor cf1 0603 1 nf 1 nf 1 nf 1 nf 10% loop filter capacitor cf2 0603 100 pf 68 pf 150 pf 82 pf 5% loop filter capacitor cx1 0805 8.2 pf 10 pf 12 pf 12 pf 5% ro capacitor for fsk ( f = 20 khz) cx2 0805 150 pf 56 pf 18 pf 15 pf 5% ro capacitor for fsk ( f = 20 khz) crx0 0603 100 pf 100 pf 100 pf 100 pf 5% rx coupling capacitor ctx0 0603 10 pf 10 pf 10 pf 10 pf 5% tx coupling capacitor ctx1 0603 10 pf 6.8 pf 5.6 pf 4.7 pf 5% tx impedance matching capacitor ctx2 0603 10 pf 6.8 pf 3.9 pf 3.9 pf 5% tx impedance matching capacitor ctx4 0603 12 pf 4.7 pf 2.2 pf 1.8 pf 5% tx impedance matching capacitor rb1 0603 100 100 100 100 5% protection resistor rf 0603 33 k 33 k 33 k 33 k 5% loop filter resistor rp 0603 3.3 k 3.3 k 3.3 k 3.3 k 5% cerdis loading resistor rl0 0603 390 390 390 390 5% cerfil loading, optionally rps 0603 18 k 33 k 43 k 43 k 5% power-select resistor rs1...rs3 0603 10 k 10 k 10 k 10 k 5% protection resistor l0 0603 56 nh 33 nh 4.7 nh 3.9 nh 5% vco tank inductor from wrth-elektronik (we-ki series) or equivalent part l1 0603 33 nh 15 nh 4.7 nh 4.7 nh 5% lna output tank inductor from wrth-elektronik (we-ki series) or equivalent part lrx2 0603 82 nh 56 nh 15 nh 15 nh 5% ltx0 0603 15 nh 15 nh 3.9 nh 3.9 nh 5% ltx1 0603 33 nh 33 nh 10 nh 10 nh 5% impedance matching inductor from wrth-elektronik (we-ki series) or equivalent part xtal hc49 smd 7x5 7.1505 mhz 20ppm cal., 20ppm temp. fundamental-mode crystal from: telcona/hong kong x?tals c5l7150500d10f3ehk02 cerfil smd 3.45x3.1 sfecf10m7ha00 b 3db = 180 khz ceramic filter from murata, or equivalent part cerdis smd 4.5x2 cdscb10m7ga136 ceramic discriminator from murata, or equivalent part note: - nip ? not in place, may be used optionally
EVB7122 27 to 930mhz transceiver evaluation board description 39012 07122 02 page 15 of 24 evb description rev. 005 june/07 4.1.2 component arrangement top side for fsk reception gnd gnd sdta vcc gnd sden sclk in dta gnd gnd gnd rssi out dta out dem ask/fsk fs1 fs0 te re ld gnd vcc melexis EVB7122_003 rx_input tx_output 1 1 1 1 1 xtal 1 3 cx2 cx1 cb7 c5 c4 rs1 rs2 rs3 cb0 1 1 11 cerdis rp cb4 c3 rl0 cb5 ctx2 ltx 1 ctx1 lrx2 crx0 ctx0 l1 c1 c2 cb1 rps cb2 ctx4 ltx0 rf cf1 cf2 l0 cb6 rb1
EVB7122 27 to 930mhz transceiver evaluation board description 39012 07122 02 page 16 of 24 evb description rev. 005 june/07 4.2 ask application circuit programmable u ser mode (normal data slicer option) software settings for ask f ro = 8.0000mhz cpcur vcocur channel frequency rr nr rt nt rx tx rx tx 315.00 mhz 80 3043 8 315 260a 1300a 300a 900a 434.00 mhz 80 4233 8 434 260a 1300a 300a 900a 915.00 mhz 80 9043 8 915 260a 1300a 300a 900a cb7 rs3 rs2 rs1 crx0 41 2 3 gnd sdta sden sclk 41 2 3 gnd gnd out_dta in_dta out_dem 41 2 3 gnd gnd rssi gnd vcc 1 2 cb0 ctx0 fs0/sden te/sdta re/sclk ask/fsk fs1/ld 2 1 3 2 1 3 2 1 3 2 1 3 2 1 3 cb2 rf cf1 cf2 ltx0 lrx2 ctx4 l0 32 31 30 29 28 27 26 25 fs0/sden tnk_lo in_dta ask/fsk vcc_dig re/sclk gain_lna vee_if in_mix out_mix out_pa out_lna vee_lna vcc_pll vee_dig vee_pll lf fs1/ld 17 18 19 20 21 22 23 24 12 13 14 15 16 1 2 in_lna vcc_if th7122 xtal cx1 c5 c3 in_dem int2/pdo int1 out_dem rssi out_dta ro fsk_sw vee_ro 9 10 11 8 3 4 5 6 7 rl0 cerfil tx_out rx_in 50 ctx2 ctx1 ltx1 l1 c1 c2 vcc in_ifa rps cps cb1 vcc rb1 cb5 cb6 c0
EVB7122 27 to 930mhz transceiver evaluation board description 39012 07122 02 page 17 of 24 evb description rev. 005 june/07 4.2.1 board component values for ask (normal data slicer option) part size value @ 315 mhz value @ 434 mhz value @ 915 mhz tol. description c0 0603 1.8 pf 2.2 pf 1.8 pf 5% vco tank capacitor c1 0603 3.9 pf 4.7 pf 1 pf 5% lna output tank capacitor c2 0603 1.5 pf 1.0 pf 1.5 pf 5% mix input matching capacitor c3 0603 10 nf 10 nf 10 nf 10% data slicer capacitor c5 0603 1.5 nf 1.5 nf 1.5 nf 10% rssi output low pass capacitor cb0 1210 10 f 10 f 10 f 20% de-coupling capacitor cb1 0603 10 nf 10 nf 10 nf 10% de-coupling capacitor cb2 0603 330 pf 330 pf 330 pf 10% de-coupling capacitor cb5 0603 100 nf 100 nf 100 nf 10% de-coupling capacitor cb6 0603 100 pf 100 pf 100 pf 10% de-coupling capacitor cb7 0603 100 nf 100 nf 100 nf 10% de-coupling capacitor cf1 0603 100 pf 100 pf 100 pf 10% loop filter capacitor cf2 0603 39 pf 39 pf 39 pf 5% loop filter capacitor cps 0603 1 nf 1 nf 1 nf 10% power-select capacitor cx1 0805 18 pf 18 pf 18 pf 5% ro capacitor crx0 0603 100 pf 100 pf 10 pf 5% rx coupling capacitor ctx0 0603 10 pf 10 pf 10 pf 5% tx coupling capacitor ctx1 0603 10 pf 6.8 pf 4.7 pf 5% tx impedance matching capacitor ctx2 0603 10 pf 6.8 pf 3.9 pf 5% tx impedance matching capacitor ctx4 0603 12 pf 4.7 pf 1.8 pf 5% tx impedance matching capacitor rb1 0603 100 100 100 5% protection resistor rf 0603 33 k 33 k 33 k 5% loop filter resistor rp 0603 3.3 k 3.3 k 3.3 k 5% cerdis loading resistor rl0 0603 390 390 390 5% cerfil loading, optionally rps 0603 18 k 33 k 43 k 5% power-select resistor rs1...rs3 0603 10 k 10 k 10 k 5% protection resistor l0 0603 47 nh 27 nh 3.9 nh 5% vco tank inductor from wrth-elektronik (we-ki series) or equivalent part l1 0603 33 nh 15 nh 4.7 nh 5% lna output tank inductor from wrth-elektronik (we-ki series) or equivalent part lrx2 0603 82 nh 56 nh 15 nh 5% ltx0 0603 15 nh 15 nh 3.9 nh 5% ltx1 0603 33 nh 33 nh 10 nh 5% impedance matching inductor from wrth-elektronik (we-ki series) or equivalent part xtal hc49 smd 7x5 8.0000 mhz 20ppm cal., 20ppm temp. fundamental-mode crystal from: telcona/hong kong x?tals c5l8000000d10f3ehk01 cerfil smd 3.45x3.1 sfecf10m7ha00 b 3db = 180 khz ceramic filter from murata, or equivalent part
EVB7122 27 to 930mhz transceiver evaluation board description 39012 07122 02 page 18 of 24 evb description rev. 005 june/07 4.2.2 component arrangement top side for ask reception (normal data slicer option) gnd gnd sdta vcc gnd sden sclk in dta gnd gnd gnd rssi out dta out dem ask/fsk fs1 fs0 te re ld gnd vcc melexis EVB7122_003 rx_input tx_output 1 1 1 1 1 xtal 1 3 cx1 cb7 c5 rs1 rs2 rs3 cb0 1 1 11 c3 rl0 cb5 ctx2 ltx 1 ctx1 lrx2 crx0 ctx0 l1 c1 c2 cb1 rps cps cb2 ctx4 ltx0 rf cf1 cf2 l0 cb6 rb1 board size is 39.5mm x 56.5mm c0
EVB7122 27 to 930mhz transceiver evaluation board description 39012 07122 02 page 19 of 24 evb description rev. 005 june/07 4.3 ask application circui t with peak detector option software settings for ask f ro = 8.0000mhz cpcur vcocur channel frequency rr nr rt nt rx tx rx tx 315.00 mhz 80 3043 8 315 260a 1300a 300 a 900a 434.00 mhz 80 4233 8 434 260a 1300a 300 a 900a 915.00 mhz 80 9043 8 915 260a 1300a 300 a 900a cb7 rs3 rs2 rs1 crx0 41 2 3 gnd sdta sden sclk 41 2 3 gnd gnd out_dta in_dta out_dem 41 2 3 gnd gnd rssi gnd vcc 1 2 cb0 ctx0 fs0/sden te/sdta re/sclk ask/fsk fs1/ld 2 1 3 2 1 3 2 1 3 2 1 3 2 1 3 cb2 rf cf1 cf2 ltx0 lrx2 ctx4 l0 32 31 30 29 28 27 26 25 fs0/sden tnk_lo in_dta ask/fsk vcc_dig re/sclk gain_lna vee_if in_mix out_mix out_pa out_lna vee_lna vcc_pll vee_dig vee_pll lf fs1/ld 17 18 19 20 21 22 23 24 12 13 14 15 16 1 2 in_lna vcc_if th7122 xtal cx1 c5 in_dem int2/pdo int1 out_dem rssi out_dta ro fsk_sw vee_ro 9 10 11 8 3 4 5 6 7 rl0 cerfil tx_out rx_in 50 ctx2 ctx1 ltx 1 l1 c1 c2 vcc in_ifa rps cps cb1 vcc rb1 cb5 c6 r2 r1 cb6 c0
EVB7122 27 to 930mhz transceiver evaluation board description 39012 07122 02 page 20 of 24 evb description rev. 005 june/07 4.3.1 board component values for ask (peak detector option) part size value @ 315 mhz value @ 434 mhz value @ 915 mhz tol. description c0 0603 1.8 pf 2.2 pf 1.8 pf 5% vco tank capacitor c1 0603 3.9 pf 4.7 pf 1 pf 5% lna output tank capacitor c2 0603 1.5 pf 1.0 pf 1.5 pf 5% mix input matching capacitor c5 0603 1.5 nf 1.5 nf 1.5 nf 10% rssi output low pass capacitor c6 0603 100 nf 100 nf 100 nf 10% pkdet capacitor cb0 1210 10 f 10 f 10 f 20% de-coupling capacitor cb1 0603 10 nf 10 nf 10 nf 10% de-coupling capacitor cb2 0603 330 pf 330 pf 330 pf 10% de-coupling capacitor cb5 0603 100 nf 100 nf 100 nf 10% de-coupling capacitor cb6 0603 100 pf 100 pf 100 pf 10% de-coupling capacitor cb7 0603 100 nf 100 nf 100 nf 10% de-coupling capacitor cf1 0603 100 pf 100 pf 100 pf 10% loop filter capacitor cf2 0603 39 pf 39 pf 39 pf 5% loop filter capacitor cps 0603 1 nf 1 nf 1 nf 10% power-select capacitor cx1 0805 18 pf 18 pf 18 pf 5% ro capacitor crx0 0603 100 pf 100 pf 10 pf 5% rx coupling capacitor ctx0 0603 10 pf 10 pf 10 pf 5% tx coupling capacitor ctx1 0603 10 pf 6.8 pf 4.7 pf 5% tx impedance matching capacitor ctx2 0603 10 pf 6.8 pf 3.9 pf 5% tx impedance matching capacitor ctx4 0603 12 pf 4.7 pf 1.8 pf 5% tx impedance matching capacitor r1 0603 100 k 100 k 100 k 5% pkdet resistor r2 0603 680 k 680 k 680 k 5% pkdet resistor rb1 0603 100 100 100 5% protection resistor rf 0603 33 k 33 k 33 k 5% loop filter resistor rp 0603 3.3 k 3.3 k 3.3 k 5% cerdis loading resistor rl0 0603 390 390 390 5% cerfil loading, optionally rps 0603 18 k 33 k 43 k 5% power-select resistor rs1...rs3 0603 10 k 10 k 10 k 5% protection resistor l0 0603 47 nh 27 nh 3.9 nh 5% vco tank inductor from wrth-elektronik (we-ki series) or equivalent part l1 0603 33 nh 15 nh 4.7 nh 5% lna output tank inductor from wrth-elektronik (we-ki series) or equivalent part lrx2 0603 82 nh 56 nh 15 nh 5% ltx0 0603 15 nh 15 nh 3.9 nh 5% ltx1 0603 33 nh 33 nh 10 nh 5% impedance matching inductor from wrth-elektronik (we-ki series) or equivalent part xtal hc49 smd 7x5 8.0000 mhz 20ppm cal., 20ppm temp. fundamental-mode crystal from: telcona/hong kong x?tals c5l8000000d10f3ehk01 cerfil smd 3.45x3.1 sfecf10m7ha00 b 3db = 180 khz ceramic filter from murata, or equivalent part
EVB7122 27 to 930mhz transceiver evaluation board description 39012 07122 02 page 21 of 24 evb description rev. 005 june/07 4.3.2 component arrangement top side for ask reception (peak detector option) gnd gnd sdta vcc gnd sden sclk in dta gnd gnd gnd rssi out dta out dem ask/fsk fs1 fs0 te re ld gnd vcc melexis EVB7122_003 rx_input tx_output 1 1 1 1 1 xtal 1 3 cx1 cb7 c5 rs1 rs2 rs3 cb0 1 1 11 rl0 cb5 ctx2 ltx 1 ctx1 lrx2 crx0 ctx0 l1 c1 c2 cb1 rps cb2 ctx4 ltx0 rf cf1 cf2 l0 cb6 rb1 r1 r2 c6 board size is 39.5mm x 56.5mm c0 cps
EVB7122 27 to 930mhz transceiver evaluation board description 39012 07122 02 page 22 of 24 evb description rev. 005 june/07 5 evaluation board layouts ? board layout data in gerber format is available, board size is 39.5mm x 56.5mm. 6 board variants type frequency/mhz modulation board execution EVB7122 ?315 ?fsk ?a antenna version ?433 ?ask according to section 4.2 / 4.3 ?c connector version ?868 ?fm ?915 note: available evb setups gnd gnd sdta vcc gnd sden sclk in dta gnd gnd gnd rssi out dta out dem ask/fsk fs1 fs0 te re ld gnd vcc melexis EVB7122_003 pcb top view pcb bottom view
EVB7122 27 to 930mhz transceiver evaluation board description 39012 07122 02 page 23 of 24 evb description rev. 005 june/07 7 package description the device th7122 is rohs compliant. fig. 4: lqfp32 (low profile quad flat package) all dimension in mm, coplanarty < 0.1mm e1, d1 e, d a a1 a2 e b c l min 1.40 0.05 1.35 0.30 0.09 0.45 0 max 7.00 9.00 1.60 0.15 1.45 0.8 0.45 0.20 0.75 7 all dimension in inch, coplanarty < 0.004? min 0.055 0.002 0.053 0.012 0.0035 0.018 0 max 0.276 0.354 0.063 0.006 0.057 0.031 0.018 0.0079 0.030 7 7.1 soldering information ? the device th7122 is qualified for msl3 with soldering peak temperature 260 deg c according to jedec j-std-20 1 32 25 17 24 8 9 16 d d1 e1 e b e a2 a a1 l c 0.25 (0.0098) 12 1 + 12 1 + .10 (.004)
EVB7122 27 to 930mhz transceiver evaluation board description 39012 07122 02 page 24 of 24 evb description rev. 005 june/07 8 disclaimer 1) the information included in this documentation is subject to melexis intellectual and other property rights. reproduction of information is permissible only if the information will not be altered and is accom- panied by all associated conditions, limitations and notices. 2) any use of the documentation wit hout the prior written consent of me lexis other than the one set forth in clause 1 is an unfair and deceptive business practice. me lexis is not responsible or liable for such al- tered documentation. 3) the information furnished by melexis in this document ation is provided ?as is?. except as expressly war- ranted in any other applicable license agreement, melexi s disclaims all warranties either express, im- plied, statutory or otherwise incl uding but not limited to the merchantab ility, fitness for a particular pur- pose, title and non-infringement with regard to the content of this documentation. 4) notwithstanding the fact that me lexis endeavors to take care of t he concept and content of this docu- mentation, it may include technical or factual inaccu racies or typographical errors. melexis disclaims any responsibility in connection herewith. 5) melexis reserves the right to change the documentat ion, the specifications and prices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with melexis for current information. 6) melexis shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special in- cidental or consequential damages, of any kind, in connec tion with or arising out of the furnishing, per- formance or use of the information in this documentation. 7) the product described in this documentation is in tended for use in normal commercial applications. ap- plications requiring operation beyond ranges specified in this documentation, unusual environmental re- quirements, or high reliability applications, such as military, medical life-support or life-sustaining equip- ment are specifically not recommended without additi onal processing by melexis for each application. 8) any supply of products by melexis will be gov erned by the melexis terms of sale, published on www.melexis.com . ? melexis nv. all rights reserved. for the latest version of this document, go to our website at: www.melexis.com or for additional information contact melexis direct: europe, africa: americas: asia: phone: +32 1367 0495 phone: +1 603 223 2362 phone: +32 1367 0495 e-mail: sales_europe@melexis.com e-mail: sales_usa@melexis.com e-mail: sales_asia@melexis.com iso/ts 16949 and iso14001 certified

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